Logic simulation is an essential step in the design flow of electronic circuits. Logic simulation is usually performed with Electronic Design Automation (EDA) software tools referred to as logic simulators, which process hardware designs typically provided in the form of Hardware Description Language (HDL) code. Hardware designers perform extensive logic simulations to verify that a hardware design complies with its specifications, before committing the hardware design to the physical implementation phase that produces the actual electronic circuit. In a typical hardware design flow, a functional verification process is carried out along with the design process in order to minimize the risk of producing a circuit that is not compliant with its specifications. A logic simulation typically generates as its results the waveforms of a set of circuit signals the user is interested in observing. The user can analyze and visualize the generated waveforms to verify that the hardware design operates correctly. Logic simulators also support simulating hardware designs with embedded assertions, which use the values of the circuit signals to detect conditions resulting in circuit malfunctioning. A logic simulator evaluates such assertions while simulating the circuit, and reports their violations to the user. Based on these violation reports, the user can uncover and fix design errors in the hardware design.
The result of insufficient or inaccurate verification of an electronic circuit can be an implemented circuit not compliant with its specifications, which can lead to customer dissatisfaction, revenue loss, increased time-to-market, and additional design and manufacturing effort. In a modern verification process a hardware description is typically verified against its specifications by testing its behavior with a large set of tests. Each test generates a set of circuit stimuli, which are used as inputs to the circuit design. A verification process can include as many as several hundred thousands of tests. New tests are added as new features are introduced in the circuit design while existing tests may be randomized to provide variation in the generated stimuli each time they are executed. A verification process is typically executed both periodically (e.g., nightly) and before finalizing recent changes made to the circuit design.
Functional verification is a major contributor to a circuit design's time to market. The amount of time required for functional verification may account for up to 70% of the design time. Most functional verification is performed using logic simulation. The exponential increase in complexity of electronic circuit designs exposes the limitations of state-of-the-art logic simulators. The common practice of increasing the computing power of simulation workstations is inadequate to keep up with the exponentially increased gate count of modern circuit designs. Shorter design turn-around and increased circuit complexity require great acceleration in the operations of logic simulators. Existing solutions, however, are usually very inefficient in situations where multiple simulations are required for a circuit.